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A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. Corpus ID: 114994830; Design of Low Power High Performance SOI Dram Cell @inproceedings{Harsimranjot2010DesignOL, title={Design of Low Power High Performance SOI Dram Cell}, author={Harsimranjot. We value time, and we value yours — and frankly, it’s not fun to get stuck digging through to prove that. 99. This paper presents the high-performance DRAM array and logic architecture for a sub-1. To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb. 27, 2002 Sheet 3 of 5 US 6,441,436 B1 XXXXX XXXXX XXXXX XXXXX 101b XXXXX A 214 l0 la 777-7777777777777. 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